H8SX1663 datasheet(99/1158 Pages) RENESAS

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Section 2 CPU

Rev.1.00 Jun. 07, 2006 Page 47 of 1102

REJ09B0294-0100

Table 2.6

Arithmetic Operation Instructions

Instruction

Size

Function

ADD

SUB

B/W/L

(EAd)

± #IMM → (EAd), (EAd) ± (EAs) → (EAd)

Performs addition or subtraction on data between immediate data,

general registers, and memory. Immediate byte data cannot be

subtracted from byte data in a general register.

ADDX

SUBX

B/W/L

(EAd)

± #IMM ± C → (EAd), (EAd) ± (EAs) ± C → (EAd)

Performs addition or subtraction with carry on data between immediate

data, general registers, and memory. The addressing mode which

specifies a memory location can be specified as register indirect with

post-decrement or register indirect.

INC

DEC

B/W/L

± 1 → Rd, Rd ± 2 → Rd

Increments or decrements a general register by 1 or 2. (Byte operands

can be incremented or decremented by 1 only.)

ADDS

SUBS

± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd

Adds or subtracts the value 1, 2, or 4 to or from data in a general register.

DAA

DAS

Rd (decimal adjust)

→ Rd

Decimal-adjusts an addition or subtraction result in a general register by

referring to the CCR to produce 2-digit 4-bit BCD data.

MULXU

B/W

× Rs → Rd

Performs unsigned multiplication on data in two general registers: either 8

bits

× 8 bits → 16 bits, or 16 bits × 16 bits → 32 bits.

MULU

W/L

× Rs → Rd

Performs unsigned multiplication on data in two general registers: either 8

bits

× 8 bits → 16 bits, or 16 bits × 16 bits → 32 bits.

MULU/U

× Rs → Rd

Performs unsigned multiplication on data in two general registers (32 bits

× 32 bits → upper 32 bits).

MULXS

B/W

× Rs → Rd

Performs signed multiplication on data in two general registers: either 8

bits

× 8 bits → 16 bits, or 16 bits × 16 bits → 32 bits.

MULS

W/L

× Rs → Rd

Performs signed multiplication on data in two general registers: either 16

bits

× 16 bits → 16 bits, or 32 bits × 32 bits → 32 bits.

MULS/U

× Rs → Rd

Performs signed multiplication on data in two general registers (32 bits

32 bits

→ upper 32 bits).

DIVXU

B/W

÷ Rs → Rd

Performs unsigned division on data in two general registers: either 16 bits

÷ 8 bits → 8-bit quotient and 8-bit remainder, or 32 bits ÷ 16 bits → 16-bit

quotient and 16-bit remainder.

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