HD64F2149YV datasheet(215/1075 Pages) RENESAS

No. de pieza	HD64F2149YV

Descripción Electrónicos	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

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Section 7 Data Transfer Controller

Rev. 3.00 Jan 18, 2006 page 187 of 1044

REJ09B0280-0300

7.3.7

Block Transfer Mode

In block transfer mode, one operation transfers one block of data. Either the transfer source or the

transfer destination is specified as a block area.

The block size is 1 to 256. When the transfer of one block ends, the initial state of the block size

counter and the address register specified in the block area is restored. The other address register is

successively incremented or decremented, or left fixed.

From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a

CPU interrupt is requested.

Table 7.7 lists the register information in block transfer mode and figure 7.8 shows memory

mapping in block transfer mode.

Table 7.7

Name

Abbreviation

Function

DTC source address register

SAR

Transfer source address

DTC destination address register

DAR

Transfer destination address

DTC transfer count register AH

CRAH

Holds block size

DTC transfer count register AL

CRAL

Block size count

DTC transfer count register B

CRB

Transfer counter

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