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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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HD64F2149YV Datasheet(PDF) 939 Page - Renesas Technology Corp |
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HD64F2149YV Datasheet(HTML) 939 Page - Renesas Technology Corp |
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939 / 1075 page  Appendix B Internal I/O Registers Rev. 3.00 Jan 18, 2006 page 911 of 1044 REJ09B0280-0300 STR3—Status Register 3 H'FE86 HIF (XBS) STR4—Status Register 4 H'FE8E HIF (XBS) 7 DBU 0 R/W R 6 DBU 0 R/W R 5 DBU 0 R/W R 4 DBU 0 R/W R 3 C/ D 0 R R 0 OBF 0 R/(W)* R 2 DBU 0 R/W R 1 IBF 0 R R Bit Initial value Slave R/W Host R/W Output buffer full 0 [Clearing condition] When the host processor reads ODR or the slave writes 0 in the OBF bit 1 [Setting condition] When the slave processor writes to ODR User-defined bits Input buffer full 0 [Clearing condition] When the slave processor reads IDR 1 [Setting condition] When the host processor writes to IDR Command/data 0 Contents of input data register (IDR) are data 1 Contents of input data register (IDR) are a command Note: * Only 0 can be written, to clear the flag. |
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