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HD64F2149YV Datasheet(PDF) 429 Page - Renesas Technology Corp |
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HD64F2149YV Datasheet(HTML) 429 Page - Renesas Technology Corp |
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429 / 1075 page  Section 13 Timer Connection Rev. 3.00 Jan 18, 2006 page 401 of 1044 REJ09B0280-0300 Table 13.6 Examples of TCR, TCSR, TCOR, and OCRDM Settings Register Bit(s) Abbreviation Contents Description TCR in FRT 4 IEDGD 1 FRC value is transferred to ICRD on the rising edge of input capture input D (IHI signal) 1 and 0 CKS1, CKS0 01 FRC is incremented on internal clock: φ/8 TCSR in FRT 0 CCLRA 0 FRC clearing is disabled TCOR in FRT 7 ICRDMS 1 ICRD is set to the operating mode in which OCRDM is used OCRDM in FRT 7 to 0 OCRDM7 to 0 H'01 to H'FF Specifies the period during which ICRD operation is masked IHI signal (without 2fH modification) IHI signal (with 2fH modification) Mask interval ICRD + OCRDM × 2 ICRD + OCRDM FRC ICRD Figure 13.6 2fH Modification Timing Chart |
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