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HD64F2149YV Datasheet(PDF) 344 Page - Renesas Technology Corp

No. de pieza HD64F2149YV
Descripción Electrónicos  Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series
PDF  1075 Pages
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Fabricante Electrónico  RENESAS [Renesas Technology Corp]
Página de inicio  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD64F2149YV Datasheet(HTML) 344 Page - Renesas Technology Corp

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Section 11 16-Bit Free-Running Timer
Rev. 3.00 Jan 18, 2006 page 316 of 1044
REJ09B0280-0300
11.2.5
Output Compare Register DM (OCRDM)
Bit
Initial
15
0
R
14
0
R
13
0
R
12
0
R
11
0
R
10
0
R
9
0
R
8
0
R
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
value
Write
Read/
OCRDM is a 16-bit readable/writable register in which the upper 8 bits are fixed at H'00.
When the ICRDMS bit in TOCR is set to 1 and the contents of OCRDM are other than H'0000,
the operation of ICRD is changed to include the use of OCRDM. The point at which input capture
D occurs is taken as the start of a mask interval. Next, twice the contents of OCRDM is added to
the contents of ICRD, and the result is compared with the FRC value. The point at which the
values match is taken as the end of the mask interval. New input capture D events are disabled
during the mask interval.
A mask interval is not generated when the ICRDMS bit is set to 1 and the contents of OCRDM are
H'0000.
OCRDM is initialized to H'0000 by a reset and in hardware standby mode.
11.2.6
Timer Interrupt Enable Register (TIER)
Bit
Initial value
Read/Write
7
ICIAE
0
R/W
6
ICIBE
0
R/W
5
ICICE
0
R/W
4
ICIDE
0
3
OCIAE
0
R/W
0
—
1
—
2
OCIBE
0
R/W
1
OVIE
0
R/W
R/W
TIER is an 8-bit readable/writable register that enables and disables interrupts.
TIER is initialized to H'01 by a reset and in hardware standby mode.
Bit 7—Input Capture Interrupt A Enable (ICIAE): Selects whether to request input capture
interrupt A (ICIA) when input capture flag A (ICFA) in TCSR is set to 1.



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