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HD6432351 Datasheet(PDF) 218 Page - Renesas Technology Corp

No. de pieza HD6432351
Descripción Electrónicos  16-Bit Single-Chip Microcomputer
PDF  1025 Pages
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Fabricante Electrónico  RENESAS [Renesas Technology Corp]
Página de inicio  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD6432351 Datasheet(HTML) 218 Page - Renesas Technology Corp

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Section 6 Bus Controller
Rev. 3.00 Sep 15, 2006 page 184 of 988
REJ09B0330-0300
(4) Usage Notes
When DRAM space is accessed, the ICIS0 and ICIS1 bit settings are disabled. In the case of
consecutive reads between different areas, for example, if the second access is a DRAM access,
only a Tp cycle is inserted, and a TI cycle is not. The timing in this case is shown in figure 6.34.
However, in burst access in RAS down mode these settings are enabled, and an idle cycle is
inserted. The timing in this case is shown in figures 6.35 (a) and (b).
T1
Address bus
φ
RD
External read
Data bus
T2
T3
Tp
Tr
DRAM space read
Tc1
Tc2
Figure 6.34 Example of DRAM Access after External Read



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