H8S2245 datasheet(163/818 Pages) RENESAS

163 / 818 page

Section 5 Interrupt Controller

Rev.3.00 Mar. 26, 2007 Page 121 of 772

REJ09B0355-0300

5.4.3

Interrupt Control Mode 1

Three-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts

by means of the I and UI bits in the CPU's CCR, and ICR.

• Control level 0 interrupt requests are enabled when the I bit is cleared to 0, and disabled when

set to 1.

• Control level 1 interrupt requests are enabled when the I bit or UI bit is cleared to 0, and

disabled when both the I bit and the UI bit are set to 1.

For example, if the interrupt enable bit for an interrupt request is set to 1, and H'20, H'00, and H'00

are set in ICRA, ICRB, and ICRC, respectively, (i.e. IRQ2 and IRQ3 interrupts are set to control

level 1 and other interrupts to control level 0), the situation is as follows:

• When I = 0, all interrupts are enabled

(Priority order: NMI > IRQ2 > IRQ3 > IRQ0 ...)

• When I = 1 and UI = 0, only NMI, IRQ2, and IRQ3 interrupts are enabled

• When I = 1 and UI = 1, only NMI interrupts are enabled

Figure 5.6 shows the state transitions in these cases.

Only NMI interrupts enabled

All interrupts enabled

Exception handling execution

or I

← 1, UI ← 1

← 0

← 1, UI ← 0

← 0

Exception handling execution

or UI

← 1

Only NMI, IRQ2, and

IRQ3 interrupts enabled

Figure 5.6 Example of State Transitions in Interrupt Control Mode 1

Figure 5.7 shows a flowchart of the interrupt acceptance operation in this case.

H8S2245 Datasheet(PDF) 163 Page - Renesas Technology Corp