M32CSLASH8B datasheet(325/406 Pages) RENESAS

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M32C/8B Group

23. Flash Memory

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 308 of 385

23.6.1

CPU Rewrite Mode

In CPU rewrite mode, the user ROM area can be programmed by the CPU writing software commands with the

MCU mounted on a board. In CPU rewrite mode, only the user ROM area shown in Figure 23.1 can be

programmed. The boot ROM area cannot be rewritten. EW0 mode and EW1 mode are provided as CPU rewrite

mode. Prior to accessing registers FMR0 to FMR3 or to entering CPU rewrite mode (EW0, EW1 mode), set the

CPU clock frequency to 10 MHz or lower using bits MCD4 to MCD0 in the MCD register, and also set the PM12

bit in the PM1 register to 1 (1 wait state).

Table 23.4 lists specifications of EW0 mode and EW1 mode. Figure 23.7 shows a setting procedure for EW0 mode.

Figure 23.8 shows a setting procedure for EW1 mode.

Table 23.4

Specifications of EW0 Mode and EW1 Mode

NOTES:

1. In both the EW0 mode and EW1 mode, when an NMI interrupt or watchdog timer interrupt is generated, the

erase or program operation in progress is aborted and the interrupt is acknowledged.

2. To use peripheral function interrupts, place interrupt routine programs and the relocatable vector table in an

area other than flash memory.

3. Do not generate an interrupt (except NMI interrupt and watchdog timer interrupt) or a DMA or DMACII transfer

during erase or program operation.

4. When the FMR31 bit in the FMR3 register is 0 (read through the data bus).

Item

EW0 Mode

EW1 Mode

Operation

• Program the user ROM area by executing

the rewrite control program placed in an

area other than the flash memory.

• Erase and program a block where the

rewrite control program is not placed, by

executing the rewrite control program

placed in the user ROM area.

Processor mode

• Single-chip mode

• Memory expansion mode

• Single-chip mode

Areas where a rewrite

program can be stored

• User ROM area

Software command

All commands are available

• Program command and block erase

command cannot be executed to the

block storing a rewrite control program

• Read status register command cannot be

executed

• Read lock bit status command(4),

read protect bit status command are

executed in the RAM

Flash memory mode after

erasing or programming

Read status register mode

Read array mode

Flash memory status

detection

• Read bits FMR00, FMR06, and FMR07 in

the FMR0 register by a program

• Execute the read status register

command to read bits SR7, SR5, and

SR4 in the SRD register

• Read bits FMR00, FMR06, and FMR07 in

the FMR0 register by a program

CPU status during erase

or program operation

Operating

In a hold state (CPU stops)

(I/O port maintains the status which is

before executing a command)

Peripheral interrupt

request, DMA request,

and DMACII request

during erase or program

operation

Acknowledged(2)

Not acknowledged(3)

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