Active edge (programmable polarity)

Active edge (programmable polarity)

Active edge (programmable polarity)

128 T

ODDEVEN

(see Note 1)

VSYNC

HSYNC

(see Note 2)

Line Numbers :

SMPTE-525

CCIR-625

4

1

5

2

6

3

266

313

267

314

268

315

269

316

Notes : 1. When ODDEVEN is a sync input, only one edge (“the active edge”) of the incoming ODDEVEN is taken into account for

synchronization. The “non-active” edge (2nd edge on this drawing) is not critical and its position may differ by H/2 from the location

shown.

2. The HSYNC pulse width indicated is valid when the STV0118 supplies HSYNC. In those slave modes where it receives HSYNC,

only the edge defined as active is relevant, and the width of the HSYNC pulse it receives is not critical.

Figure 9 : ODDEVEN, VSYNC and HSYNC Waveforms

HSYNC

(out)

ODDEVEN

(out)

CKREF

YCRCB

Cb

Y

Cr

Y’

Active Edge

(programmable polarity)

Active Edge

(programmable polarity)

1T

CKREF

Duration of HSYNC Pulse : 128 T

CKREF

Cr

Y’

Note :

1. This figure is valid for bits “syncout_ad[1:0]” = default.

Figure 10 : Master Mode Sync Signals

IV - FUNCTIONAL DESCRIPTION (continued)

IV.4 - Master Mode

In this mode, the STV0118 supplies HSYNC and

ODDEV sync signals (with independentlyprogram-

mable polarities) to drive other blocks. Refer to

Figure 9 and 10 for timings and waveforms.

The STV0118 starts encoding and counting clock

cycles as soon as the master mode has been

loaded into the control register (Reg.0).

Configurationbits “Syncout_ad[1:0]”(Reg4)allow to

shift the relative position of the sync signals by up

to 3 clock cycles to cope with any YCrCb phasing.

STV0118

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