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HD151TS206SS Datasheet(PDF) 7 Page - Renesas Technology Corp

No. de pieza HD151TS206SS
Descripción Electrónicos  Mother Board Clock Generator for Intel P4 Chipset (Springdale)
PDF  34 Pages
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Fabricante Electrónico  RENESAS [Renesas Technology Corp]
Página de inicio  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD151TS206SS Datasheet(HTML) 7 Page - Renesas Technology Corp

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HD151TS206SS
Rev.1.00, Apr.28.2003, page 7 of 34
I
2C Controlled Register Bit Map
Byte0 Control Register
Bit
Description
Contents
Type
Default
Note
7
Reserved
R
0
6
Reserved
R
0
5
Reserved
R
0
4
Reserved
R
0
3
Reserved
R
1
2
Reserved
R
1
1
Reserved
R
X
0
Reserved
R
X
Byte1 Control Register
Bit
Description
Contents
Type
Default
Note
7
Reserved
RW
0
6
SRC Output enable
0 = Disabled (tristate)
1 = Enabled
RW
1
5
Reserved
RW
1
4
Reserved
RW
1
3
Reserved
RW
1
2
CPU2 Output enable
0 = Disabled (tristate)
1 = Enabled
RW
1
1
CPU1 Output enable
0 = Disabled (tristate)
1 = Enabled
RW
1
0
CPU0 Output enable
0 = Disabled (tristate)
1 = Enabled
RW
1
Byte2 Control Register
Bit
Description
Contents
Type
Default
Note
7
SRC_Pwrdwn drive mode
0 = Driven in power down, 1 = Tristate
RW
0
6
Reserved
RW
0
See
Table
2
5
CPU2_Pwrdwn drive mode
0 = Driven in power down, 1 = Tristate
RW
0
4
CPU1_Pwrdwn drive mode
0 = Driven in power down, 1 = Tristate
RW
0
3
CPU0_Pwrdwn drive mode
0 = Driven in power down, 1 = Tristate
RW
0
2
Reserved
RW
0
1
Reserved
RW
0
0
Reserved
RW
0
See
Table
1



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