M38047F5HKP datasheet(22/116 Pages) RENESAS

22 / 116 page

Rev.1.01

Jan 25, 2005

page 22 of 114

REJ03B0131-0101Z

3804 Group (Spec. H)

INTERRUPTS

The 3804 group (Spaec. H)’s interrupts are a type of vector and

occur by 16 sources among 23 sources: nine external, thirteen in-

ternal, and one software.

Interrupt Control

Each interrupt is controlled by an interrupt request bit, an interrupt

enable bit, and the interrupt disable flag except for the software in-

terrupt set by the BRK instruction. An interrupt occurs if the

corresponding interrupt request and enable bits are “1” and the in-

terrupt disable flag is “0”.

Interrupt enable bits can be set or cleared by software.

Interrupt request bits can be cleared by software, but cannot be

set by software.

The reset and the BRK instruction cannot be disabled with any

flag or bit. The I (interrupt disable) flag disables all interrupts ex-

cept the reset and the BRK instruction interrupt.

When several interrupt requests occur at the same time, the inter-

rupts are received according to priority.

Interrupt Operation

By acceptance of an interrupt, the following operations are auto-

matically performed:

1. The contents of the program counter and the processor status

2. The interrupt disable flag is set and the corresponding interrupt

request bit is cleared.

3. The interrupt jump destination address is read from the vector

table into the program counter.

Interrupt Source Selection

Which of each combination of the following interrupt sources can

be selected by the interrupt source selection register (address

003916).

1. INT0 or Timer Z

2. Serial I/O1 transmission or SCL, SDA

3. CNTR0 or SCL, SDA

4. CNTR1 or Serial I/O3 reception

5. Serial I/O2 or Timer Z

6. INT2 or I2C

7. INT4 or CNTR2

8. A/D converter or serial I/O3 transmission

External Interrupt Pin Selection

The occurrence sources of the external interrupt INT0 and INT4

can be selected from either input from INT00 and INT40 pin, or in-

put from INT01 and INT41 pin by the INT0, INT4 interrupt switch bit

of interrupt edge selection register (bit 6 of address 003A16).

s Notes

When setting the followings, the interrupt request bit may be set to

“1”.

•When setting external interrupt active edge

Related register: Interrupt edge selection register (address 003A16)

Timer XY mode register (address 002316)

Timer Z mode register (address 002A16)

I2C START/STOP condition control register

(address 001616)

•When switching interrupt sources of an interrupt vector address

where two or more interrupt sources are allocated

Related register: Interrupt source selection register

(address 003916)

When not requiring for the interrupt occurrence synchronized with

these setting, take the following sequence.

➀Set the corresponding interrupt enable bit to “0” (disabled).

➁Set the interrupt edge select bit or the interrupt source select bit

to “1”.

➂Set the corresponding interrupt request bit to “0” after 1 or more

instructions have been executed.

{Set the corresponding interrupt enable bit to “1” (enabled).

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