M38042F2HKP datasheet(55/116 Pages) RENESAS

55 / 116 page

Rev.1.01

Jan 25, 2005

page 55 of 114

REJ03B0131-0101Z

3804 Group (Spec. H)

A/D CONVERTER

[AD Conversion Register 1, 2 (AD1, AD2)]

003516, 003816

The AD conversion register is a read-only register that stores the

result of an A/D conversion. When reading this register during an

A/D conversion, the previous conversion result is read.

Bit 7 of the AD conversion register 2 is the conversion mode se-

lection bit. When this bit is set to “0,” the A/D converter becomes

the 10-bit A/D mode. When this bit is set to “1,” that becomes the

8-bit A/D mode. The conversion result of the 8-bit A/D mode is

stored in the AD conversion register 1. As for 10-bit A/D mode, not

only 10-bit reading but also only high-order 8-bit reading of con-

version result can be performed by selecting the reading

procedure of the AD conversion registers 1, 2 after A/D conversion

is completed (in Figure 50).

As for 10-bit A/D mode, the 8-bit reading inclined to MSB is per-

formed when reading the AD converter register 1 after A/D

conversion is started; and when the AD converter register 1 is

read after reading the AD converter register 2, the 8-bit reading in-

clined to LSB is performed.

[AD/DA Control Register (ADCON)] 003416

The AD/DA control register controls the A/D conversion process.

Bits 0 to 2 and bit 4 select a specific analog input pin. Bit 3 signals

the completion of an A/D conversion. The value of this bit remains

at “0” during an A/D conversion, and changes to “1” when an A/D

conversion ends. Writing “0” to this bit starts the A/D conversion.

Comparison Voltage Generator

The comparison voltage generator divides the voltage between

VREF and AVSS into 1024, and that outputs the comparison voltage

in the 10-bit A/D mode (256 division in 8-bit A/D mode).

The A/D converter successively compares the comparison voltage

Vref in each mode, dividing the VREF voltage (see below), with the

input voltage.

• 10-bit A/D mode (10-bit reading)

Vref =

✕ n (n = 0–1023)

• 10-bit A/D mode (8-bit reading)

Vref =

✕ n (n = 0–255)

• 8-bit A/D mode

Vref =

✕ (n–0.5) (n = 1–255)

(n = 0)

Fig. 49 Structure of AD/DA control register

Channel Selector

The channel selector selects one of ports P67/AN7 to P60/AN0 or

P07/AN15 to P00/AN8, and inputs the voltage to the comparator.

Comparator and Control Circuit

The comparator and control circuit compares an analog input volt-

age with the comparison voltage, and then stores the result in the

AD conversion registers 1, 2. When an A/D conversion is com-

pleted, the control circuit sets the AD conversion completion bit

and the AD interrupt request bit to “1”.

Note that because the comparator consists of a capacitor cou-

pling, set f(XIN) to 500 kHz or more during an A/D conversion.

VREF

256

VREF

256

Fig. 50 Structure of 10-bit A/D mode reading

VREF

1024

AD/DA control register

(ADCON : address 003416)

Analog input pin selection bits 1

0 0 0: P60/AN0 or P00/AN8

0 0 1: P61/AN1 or P01/AN9

0 1 0: P62/AN2 or P02/AN10

0 1 1: P63/AN3 or P03/AN11

1 0 0: P64/AN4 or P04/AN12

1 0 1: P65/AN5 or P05/AN13

1 1 0: P66/AN6 or P06/AN14

1 1 1: P67/AN7 or P07/AN15

AD conversion completion bit

0: Conversion in progress

1: Conversion completed

Analog input pin selection bit 2

0: AN0 to AN7 side

1: AN8 to AN15 side

Not used (returns “0” when read)

DA1 output enable bit

0: DA1 output disabled

1: DA1 output enabled

DA2 output enable bit

0: DA2 output disabled

1: DA2 output enabled

b2 b1 b0

10-bit reading

(Read address 003816 before 003516)

AD conversion register 2

(AD2: address 003816)

AD conversion register 1

(AD1: address 003516)

8-bit reading

(Read only address 003516)

AD conversion register 1

(AD1: address 003516)

Note : Bits 2 to 6 of address 003816 become “0”

at reading.

b7 b6 b5 b4 b3 b2 b1 b0

b9 b8 b7 b6 b5 b4 b3 b2

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