HD151TS307ARP

Rev.4.00 Jul. 08, 2004 page 5 of 8

tcycle n

t

= (tcycle n) - (tcycle n+1)

CCS

tcycle n+1

SSCCLKOUT

Figure 1 Cycle to cycle jitter

Application Information

1. Recommended Circuit Configuration

The power supply circuit of the optimal performance on the application of a system should refer to Fig. 2.

VDD decoupling is important to both reduce Jitter and EMI radiation.

The C1 decoupling capacitor should be placed as close to the VDD pin as possible, otherwise the increased trace

inductance will negate its decoupling capability.

The C2 decoupling capacitor shown should be a tantalum type.

8

1

7

SSCCLKOUT

6

SEL0

SEL1

NC

5

2

3

4

XIN

XOUT

R1

C1

C2

GND GND

GND

VDD

(Crystal or

Reference input)

(Crystal or

Not connection)

Notes:

C1 = High frequency supply decoupling capacitor.

(0.1

µF recommended)

C2 = Low frequency supply decoupling capacitor.

(22

µF tantalum type recommended)

R1 = Match value to line impedance.

(22

Ω Reference value)

Figure 2 Recommended circuit configuration