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ST72334J2TA/XXX Datasheet(PDF) 97 Page - STMicroelectronics |
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ST72334J2TA/XXX Datasheet(HTML) 97 Page - STMicroelectronics |
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97 / 150 page  ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto 97/150 SERIAL COMMUNICATIONS INTERFACE (Cont’d) EXTENDED RECEIVE PRESCALER DIVISION REGISTER (ERPR) Read/Write Reset Value: 0000 0000 (00h) Allows setting of the Extended Prescaler rate divi- sion factor for the receive circuit. Bit 7:1 = ERPR[7:0] 8-bit Extended Receive Pres- caler Register. The extended Baud Rate Generator is activated when a value different from 00h is stored in this register. Therefore the clock frequency issued from the 16 divider (see Figure 49) is divided by the binary factor set in the ERPR register (in the range 1 to 255). The extended baud rate generator is not used af- ter a reset. EXTENDED TRANSMIT PRESCALER DIVISION REGISTER (ETPR) Read/Write Reset Value:0000 0000 (00h) Allows setting of the External Prescaler rate divi- sion factor for the transmit circuit. Bit 7:1 = ETPR[7:0] 8-bit Extended Transmit Pres- caler Register. The extended Baud Rate Generator is activated when a value different from 00h is stored in this register. Therefore the clock frequency issued from the 16 divider (see Figure 49) is divided by the binary factor set in the ETPR register (in the range 1 to 255). The extended baud rate generator is not used af- ter a reset. Table 19. SCI Register Map and Reset Values 7 0 ERPR 7 ERPR 6 ERPR 5 ERPR 4 ERPR 3 ERPR 2 ERPR 1 ERPR 0 7 0 ETPR 7 ETPR 6 ETPR 5 ETPR 4 ETPR 3 ETPR 2 ETPR 1 ETPR 0 Address (Hex.) Register Label 7 6 5 4 3 2 1 0 0050h SCISR Reset Value TDRE 1 TC 1 RDRF 0 IDLE 0 OR 0 NF 0 FE 0 0 0051h SCIDR Reset Value MSB x x x x x x x LSB x 0052h SCIBRR Reset Value SOG 0 0 VPOL x 2FHDET x HVSEL x VCORDIS x CLPINV x BLKINV x 0053h SCICR1 Reset Value R8 x T8 x 0 M x WAKE x 0 0 0 0054h SCICR2 Reset Value TIE 0 TCIE 0 RIE 0 ILIE 0 TE 0 RE 0 RWU 0 SBK 0 0055h SCIPBRR Reset Value MSB 0 0 0 0 0 0 0 LSB 0 0057h SCIPBRT Reset Value MSB 0 0 0 0 0 0 0 LSB 0 |
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