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LD39300 Datasheet(PDF) 4 Page - STMicroelectronics

No. de pieza LD39300
Descripción Electrónicos  Ultra low drop BICMOS voltage regulator
PDF  17 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

LD39300 Datasheet(HTML) 4 Page - STMicroelectronics

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Pin configuration
LD39300
4/17
2
Pin configuration
Figure 2.
Pin connections (top view for DPAK and PPAK)
DPAK
PPAK
Table 1.
Pin description
Pln N°
Symbol
Note
PPAK
DPAK
5
VSENSE/N.C. For fixed versions: Not Connected on PPAK
ADJ
For adjustable version: Error Amplifier Input pin for VO from 1.22 to 5.0V
21
VI
LDO Input Voltage; VI from 2.5V to 6V, CI=1µF must be located at a distance of not
more than 0.5’’ from input pin.
43
VO
LDO Output Voltage pins, with minimum CO=4.7µF needed for stability (also refer
to CO vs. ESR stability chart)
1VINH
Inhibit Input Voltage: ON MODE when VINH ≥ 2V, OFF MODE when VINH ≤0.3V
(Do not leave floating, not internally pulled down/up)
3
2
GND
Common ground



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