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74LVQ02 Datasheet(PDF) 1 Page - STMicroelectronics |
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74LVQ02 Datasheet(HTML) 1 Page - STMicroelectronics |
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1 / 11 page ![]() 1/11 July 2004 s HIGH SPEED: tPD = 5 ns (TYP.) at VCC = 3.3 V s COMPATIBLE WITH TTL OUTPUTS s LOW POWER DISSIPATION: ICC = 2µA(MAX.) at TA=25°C s LOW NOISE: VOLP = 0.3V (TYP.) at VCC = 3.3V s 75 Ω TRANSMISSION LINE DRIVING CAPABILITY s SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 12mA (MIN) at VCC = 3.0V s PCI BUS LEVELS GUARANTEED AT 24 mA s BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL s OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 3.6V (1.2V Data Retention) s PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 02 s IMPROVED LATCH-UP IMMUNITY DESCRIPTION The 74LVQ02 is a low voltage CMOS QUAD 2-INPUT NOR GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications. The internal circuit is composed of 3 stages including buffer output, which enables high noise immunity and stable output. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. 74LVQ02 LOW VOLTAGE CMOS QUAD 2-INPUT NOR GATE Figure 1: Pin Connection And IEC Logic Symbols Table 1: Order Codes PACKAGE T & R SOP 74LVQ02MTR TSSOP 74LVQ02TTR TSSOP SOP Rev. 5 |
Número de pieza similar - 74LVQ02 |
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Descripción similar - 74LVQ02 |
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