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STLC60135 Datasheet(PDF) 21 Page - STMicroelectronics

No. de pieza STLC60135
Descripción Electrónicos  TOSCA ADSL DMT TRANSCEIVER
PDF  25 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STLC60135 Datasheet(HTML) 21 Page - STMicroelectronics

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Table 3: Master Clock (MCLK) AC Electrical Characteristics
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
F
Clock Frequency
35.328
MHz
Tper
Clock Period
28.3
ns
Th
Clock Duty Cycle
40
60
%
Table 4: AFTXD, AFTXED, CLWD AC Electrical Characteristics
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Tv
Data Valid Time
0
10
ns
Tc
Data Valid Time
0
10
ns
Table 5: AFRXD AC Electrical Characteristics
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Ts
Data setup Time
5
ns
Th
Data hold Time
5
ns
Tests, Clock, JTAG Interface
- Mclk: Master Clock (35.328MHz) generated by
VCXO
- ATM receive interface, asynchronous clock gen-
erated by Utopia Master
- ATM transmit interface, asynchronous clock
generated by Utopia Master
- ATC clock (Pclk): external asynchronous clock
(synchronous with ATC in case of i960 specific in-
terface)
JTAG TP interface: Standard Test Access Port,
Used with the boundary scan for chip and board
testing.
This JTAG TAP interface consists in 5 signals:
TDI, TDO, TCK & TMS.
TSRTB: Test Reset, reset the TAP controller.
TRSTB is an active low signal.
Table 6: Boundary Scan Chain Sequence
Sequence
Number
Mnemonic
Pin
BS Type
2
AD_0
B
3
AD_1
B
4
AD_2
B
6
AD_3
B
7
AD_4
B
9
AD_5
B
10
AD_6
B
12
AD_7
B
13
AD_8
B
14
AD_9
B
16
AD_10
B
17
AD_11
B
19
AD_12
B
21
PCLK
I
23
AD_13
B
24
AD_14
B
25
AD_15
B
27
BE1
I
28
ALE
C
30
CSB
I
31
WR_RDB
I
32
RDYB
O
33
OBC_TYPE
I
34
INTB
O
35
RESETB
I
38
U_RxData_0
B
39
U_RxData_1
B
41
U_RxData_2
B
42
U_RxData_3
B
44
U_RxData_4
B
45
U_RxData_5
B
46
VSS
47
U_RxData_6
B
48
U_RxData_7
B
50
U_RxADDR_0
I
51
U_RxADDR_1
I
52
U_RxADDR_2
I
53
U_RxADDR_3
I
55
U_RxADDR_4
I
56
GP_IN_0
i
58
GP_IN_1
I
60
U_RxRefB
O
STLC60135
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