STLC5412 datasheet(21/74 Pages) STMICROELECTRONICS

21 / 74 page

Data is transmitted in both directions at half the

data clock rate. The information is clocked by the

transmitter on the front edge of the data clock and

can be accepted by the receiver after 1 to 1.5 pe-

riod of the data clock.

The data clock (BCLK) is a square wave signal at

twice the data transmission frequency on Bx and

Br with a 1 to 1 duty cycle. The frequency can be

choosen from 512

to 6176 kHz with 16 kHz

modularity. Data transmission rate depends only

on the data clock rate.

The Frame Clock FSa is a 8 kHz signal for syn-

chronization of data transmission. The front edge

of this signal gives the time reference of the first

bit in the first GCI input and output channel, and

reset the slot counter at the start of each frame.

When some GCI channels are not selected on

devices connected to the same GCI link, these

time slots are free for alternative uses.

GCI configuration selection is done by biasing of

input pins MW, M0, CONF1, CONF2 according to

Table 1.

Table 1: GCI Configuration selection.

Pin Number

Pin name

Configuration

PLCC44

DIP28

LT/NT12 (1)

NT/TE

NT1-AUTO

LT-RR-AUTO

NT-RR-AUTO

0000

0111

S1/CONF1

S2/CONF2

S0/FSb/TEST2

FSb

TEST2

IO1/ES1 (2)

IO1

ES1

PLDD

ES1

IO2/ES2 (2)

IO2

ES2

IO3/EC (2)

IO3

LFS

IO4/TEST1 (2)

IO4

TEST1

SFSx/RFS (2)

SFSx

RFS

(1) Differentation between LT and NT configuration done by bit NTS in CR2 register; GCI in slave mode.

When NT1-AUTO or NT-RR-AUTO configuration is selected, BCLK bit clock frequency of 512 kHz is

automatically selected

When NT configuration is selected, BCLK bit clock frequency of 1536 kHz is automatically selected.

(2) Connected to VCC through internal pull-up resistors.

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