STLC5411FN datasheet(42/72 Pages) STMICROELECTRONICS

42 / 72 page

and M56, both registers RXM4 and RXM56 are

queued in the interrupt register stack.

Bits act, dea, uoa, sai are dedicated to the activa-

tion procedure. Validation is always done in ac-

cordance with the ANSI rule: validation at each

new activation bit received and confirmed twice

independently from the above rules. These bits

are taken into account directly by the activation

decoder. An interrupt is not generated for the

RXM4 Register when one of these bits changes,

but they are provided for test to the RXM4 Regis-

ter.

OC1, OC0 eoc channel processing:

select how a received eoc message is validated

and transmitted to the system.

OC1

OC0

every half a super frame, an

interrupt is generated for the

RXEOC register. eoc channel

is transparently transmitted to

the system.

an interrupt is set at each new

eoc message received.

an interrupt is set at each new

eoc message received and

confirmed once. (two times

identical)

an interrupt is set at each new

eoc message received and

confirmed twice. (three times

identical).

C2E Counter 2 enable:

C2E = 0: Only counter BEC1 is used for both febe

and nebe counting.

C2E = 1: Counter BEC1 is used for nebe.

Counter BEC2 is used for febe.

Configuration register 1 (CR1)

After reset:

µW mode 00H

GCI: MO = 0 (LT/NT12) = C0H

GCI: MO = 1 (NT/TE) = D2H

FF1

FF0

CK2

CK1

CK0

DDM

CMS

BEX

FF1, FF0 Frame Format Selection: (

µW/DSI only)

Refer to fig. 2 and 3.

FF1

FF2

Format 1

Format 2

Format 3

Format 4

CK0-CK2 Digital Interface Clock select: (mW/DSI

only)

CK0-CK2 bits select the BCLK output frequency

when DSI clocks are outputs.

CK2

CK1

CK0

BCLK frequency:

256KHz

512KHz

1536KHz

2048KHz

2560KHz

DDM Delayed Data Mode select:(

µW/DSI only)

Two different phase-relations may be established

between the Frame Sync signals and the first bit

of the frame on the Digital Interface:

DDM = 0: Non delayed data mode The first bit

the

frame

begins

nominally

coincident with the rising edge of

FSA/B.

DDM = 1: delayed data mode: FSA/B input must

be set high at least a half cycle of

BCLK earlier the frame beginning.

CMS Clocks Master Select:(

µW/DSI only)

CMS = 0: BCLK, FSA and FSB are inputs;

BCLK can have in Format 1, 2 and 3

value between 256KHz to 4096KHz,

value

Format

512KHz

6176KHz.

CMS = 1: BCLK, FSA and FSB are outputs; FSA

is a 8 kHz clock pulse indicating the

frame beginning, FSB is a 8 kHz clock

pulse is indicating the second 8 bits

wide time-slot. BCLK is a bit clock

signal whose frequency bits CK2-CK0.

BEX B channels Exchange:

BEX = 0: B1

and

Tx/Rx

channels are

associated

with

TXB1/RXB1

and

TXB2/RXB2 registers respectively.

BEX = 1: B1 and B2 channels are exchanged.

Configuration register 2 (CR2)

After reset:

µW mode 00H

GCI: MO = 0 (LT/NT12) = 00H

GCI: MO = 1 (NT/TE) = 80H

µW (LT,NT):

SFS NTS DMO DEN ETC BP1

EIF

BP2

BFH9D

GCI (LT,NT):

SFS NTS T24D CID

ETC BP1

EIF

BP2

BFH9D

SFS Super Frame Synchronization Select:

Significant in LT mode only.

STLC5411

42/72

STLC5411FN Datasheet(PDF) 42 Page - STMicroelectronics

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