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74LCX74 Datasheet(PDF) 7 Page - STMicroelectronics

No. de pieza 74LCX74
Descripción Electrónicos  Low voltage CMOS dual D-Type Flip Flop with 5V tolerant inputs
PDF  17 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

74LCX74 Datasheet(HTML) 7 Page - STMicroelectronics

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74LCX74
Electrical characteristics
7/17
Table 7. AC electrical characteristics
Symbol
Parameter
Test condition
Value
Unit
VCC
(V)
CL
(pF)
RL
(
Ω)
ts = tr
(ns)
-40 to 85 °C
Min
Max
tPLH tPHL
Propagation delay
time (CK to Q or
Q)
2.7
50
500
2.5
1.5
8.0
ns
3.0 to 3.6
1.5
7.0
tPLH tPHL
Propagation delay
time (PR or CLR
to Q or Q)
2.7
50
500
2.5
1.5
8.0
ns
3.0 to 3.6
1.5
7.0
tS
Setup time, HIGH
or LOW level D to
CK
2.7
50
500
2.5
2.5
ns
3.0 to 3.6
2.5
th
Hold time, HIGH
or LOW level D to
CK
2.7
50
500
2.5
1.5
ns
3.0 to 3.6
1.5
tW
CK Pulse width,
HIGH or LOW
PR or CLR Pulse
Width, LOW
2.7
50
500
2.5
3.0
ns
3.0 to 3.6
3.0
trec
Recovery time PR
or CLR to CK
2.7
50
500
2.5
0
ns
3.0 to 3.6
0
fMAX
Clock pulse
frequency
2.7
50
500
2.5
150
MHz
tOSLH
tOSHL
Output to output
skew time (1) (2)
1.
Skew is defined as the absolute value of the difference between the actual propagation delay for any two
outputs of the same device switching in the same direction, either HIGH or LOW (tOSLH = | tPLHm - tPLHn|,
tOSHL = | tPHLm - tPHLn|)
2.
Parameter guaranteed by design
3.0 to 3.6
50
500
2.5
1.0
ns
Table 8. Capacitive characteristics
Symbol
Parameter
Test condition
Value
Unit
VCC
(V)
TA = 25 °C
Min
Typ
Max
CIN
Input capacitance
3.3
VIN = 0 to VCC
6pF
CPD
Power dissipation
capacitance (1)
1.
CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the
operating current consumption without load. (Refer to Test Circuit). Average operating current can be
obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/2 (per gate)
3.3
fIN = 10MHz
VIN = 0 or VCC
40
pF



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