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T84C5112-RKUCL Datasheet(PDF) 70 Page - ATMEL Corporation |
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T84C5112-RKUCL Datasheet(HTML) 70 Page - ATMEL Corporation |
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70 / 97 page  70 Rev. B - November 10, 2000 Preliminary T80C5112 Reset Value = XXXX X00Xb Not Bit addressable. Table 45. IPL1 Register IPL1 - Interrupt Priority Low Register 1 (S:B2h) 7 6 5 4 3 2 1 0 - - - - - PSPI PADC - Bit Number Bit Mnemonic Description 7 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit. 3 - Reserved The value read from this bit is indeterminate. Do not set this bit. 2 PSPI SPI Interrupt Priority level less significant bit. Refer to PSPIH for priority level. 1 PADC ADC Interrupt Priority level less significant bit. Refer to PADCH for priority level. 0 - Reserved The value read from this bit is indeterminate. Do not set this bit. |
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