TAS5705PAPR datasheet(7/71 Pages) TI

7 / 71 page

ABSOLUTE MAXIMUM RATINGS

TAS5705

www.ti.com ...................................................................................................................................................................................................... SLOS549 – JUNE 2008

TERMINAL FUNCTIONS (continued)

TERMINAL

5-V

TERMINATION

TYPE(1)

DESCRIPTION

TOLERANT

(2)

NAME

NO.

SCLK

5-V

Serial audio data clock (shift clock). SCLK is the serial audio port

input data bit clock.

SDA

DIO

5-V

I2C serial control data interface input/output

SDIN1

5-V

Serial audio data 1 input is one of the serial data input ports. SDIN1

supports three discrete (stereo) data formats.

SDIN2

5-V

Serial audio data 2 input is one of the serial data input ports. SDIN2

supports three discrete (stereo) data formats.

SSTIMER

Controls ramp time of OUT_X for pop-free operation. Leave this pin

floating for BD mode. Requires capacitor of 2.2 nF to GND in AD

mode. The capacitor determines the ramp time of PWM outputs from

0% to 50%. For 2.2 nF, start/stop time is ~10 ms.

STEST

Test pin. Connect directly to GND.

SUB_PWM–

Subwoofer negative PWM output

SUB_PWM+

Subwoofer positive PWM output

TEST1

Test pin. Connect directly to GND.

TEST2

Test pin. Connect directly to DVDD.

VALID

Output indicating validity of ALL PWM channels, active-high. This pin

is connected to an external power stage. If no external power stage is

used, leave this pin floating.

VR_ANA

Internally regulated 1.8-V analog supply voltage. This terminal must

not be used to power external devices.

VR_DIG

Internally regulated 1.8V digital supply voltage.This terminal must not

be used to power external devices.

VREG

3.3 Regulator output. Not to be used as s supply or connected to any

other components other than decoupling caps. Add decoupling

capacitors with pins 42 and 41.

VREG_EN

Pulldown

Voltage regulator enable. Connect directly to GND.

over operating free-air temperature range (unless otherwise noted)

(1)

VALUE

UNIT

DVDD, AVDD

–0.3 to 3.6

Supply voltage

PVDD_X

–0.3 to 30

OC_ADJ

–0.3 to 4.2

Input voltage

3.3-V digital input

–0.5 to DVDD + 0.5

5-V tolerant(2) digital input

–0.5 to DVDD + 2.5

OUT_x to PGND_X

32(3)

BST_x to PGND_X

43(3)

Input clamp current, IIK (VI < 0 or VI > 1.8 V)

±20

Output clamp current, IOK (VO < 0 or VO > 1.8 V)

±20

Operating free-air temperature

0 to 85

°C

Operating junction temperature range

0 to 150

°C

Storage temperature range, Tstg

–40 to 125

°C

(1)

Stresses beyond those listed under absolute ratings may cause permanent damage to the device. These are stress ratings only and

functional operation of the device at these or any other conditions beyond those indicated under recommended operation conditions are

not implied. Exposure to absolute-maximum conditions for extended periods may affect device reliability.

(2)

5-V tolerant inputs are PDN, RESET, MUTE, SCLK, LRCLK, MCLK, SDIN1, SDIN2, SDA, SCL, and HPSEL.

(3)

DC voltage + peak ac waveform measured at the pin should be below the allowed limit for all conditions.

Submit Documentation Feedback

Product Folder Link(s): TAS5705

TAS5705PAPR Datasheet(PDF) 7 Page - Texas Instruments

TAS5705PAPR Datasheet(HTML) 7 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71

Datasheet Descarga

Enlace URL