Motor de Búsqueda de Datasheet de Componentes Electrónicos
  Spanish  ▼
ALLDATASHEET.ES

X  

EMLS232TA Datasheet(PDF) 10 Page - Emerging Memory & Logic Solutions Inc

No. de pieza EMLS232TA
Descripción Electrónicos  512K x 32 x 4Banks Low Power SDRAM Specificaton
PDF  14 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Fabricante Electrónico  EMLSI [Emerging Memory & Logic Solutions Inc]
Página de inicio  http://www.emlsi.com
Logo EMLSI - Emerging Memory & Logic Solutions Inc

EMLS232TA Datasheet(HTML) 10 Page - Emerging Memory & Logic Solutions Inc

Back Button EMLS232TA Datasheet HTML 6Page - Emerging Memory & Logic Solutions Inc EMLS232TA Datasheet HTML 7Page - Emerging Memory & Logic Solutions Inc EMLS232TA Datasheet HTML 8Page - Emerging Memory & Logic Solutions Inc EMLS232TA Datasheet HTML 9Page - Emerging Memory & Logic Solutions Inc EMLS232TA Datasheet HTML 10Page - Emerging Memory & Logic Solutions Inc EMLS232TA Datasheet HTML 11Page - Emerging Memory & Logic Solutions Inc EMLS232TA Datasheet HTML 12Page - Emerging Memory & Logic Solutions Inc EMLS232TA Datasheet HTML 13Page - Emerging Memory & Logic Solutions Inc EMLS232TA Datasheet HTML 14Page - Emerging Memory & Logic Solutions Inc  
Zoom Inzoom in Zoom Outzoom out
 10 / 14 page
background image
Rev 0.3
EMLS232TA Series
512K x 32 x 4Banks Low Power SDRAM
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
NOTE :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1 , (tr/2-0.5)
should be added to the parameter.
3. tAC(max) value is measured at the low Vdd(2.6V) and cold temperature(-25 ).
tAC is measured in the device with half driver strength(CL=10pF) and under the AC output load condition.
4. Assumed input rise and fall time (tr & tf) = 1 .
If tr & tf is longer than 1 , transient time compensation should be considered,
i.e., [(tr + tf)/2-1]
should be added to the parameter.
Parameter
Symbol
Value
Unit
Note
Min
Max
CLK cycle time
CAS latency=3
tCC
7.5
1000
1
CAS latency=2
tCC
10
CAS latency=1
tCC
-
CLK to valid output delay
CAS latency=3
tAC
6
1,2,3
CAS latency=2
tAC
7
CAS latency=1
tAC
-
Output data hold time
CAS latency=3
tOH
2.5
2
CAS latency=2
tOH
2.5
CAS latency=1
tOH
-
CLK high pulse width
tCH
2.5
4
CLK low pulse width
tCL
2.5
4
Input setup time
tSS
2.0
4
Input hold time
tSH
1.0
4
CLK to output in Low-Z
tSLZ
1.0
2
CLK to output in Hi-Z
CAS latency=3
tSHZ
6
CAS latency=2
7
CAS latency=1
-



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14


Datasheet Descarga

Go To PDF Page


Enlace URL



¿ALLDATASHEET es útil para Ud.?  [ DONATE ] 

Todo acerca de Alldatasheet   |   Publicidad   |   Contáctenos   |   Política de Privacidad   |   Enlace a la hoja de datos    |   Intercambio de Enlaces   |   Lista de Fabricantes
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com