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ST90135 Datasheet(PDF) 141 Page - STMicroelectronics |
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ST90135 Datasheet(HTML) 141 Page - STMicroelectronics |
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141 / 190 page ![]() 141/190 ST90158 - SERIAL COMMUNICATIONS INTERFACE (SCI) 9.5 SERIAL COMMUNICATIONS INTERFACE (SCI) 9.5.1 Introduction The Serial Communications Interface (SCI) offers full-duplex serial data exchange with a wide range of external equipment. The SCI offers four operat- ing modes: Asynchronous, Asynchronous with synchronous clock, Serial expansion and Syn- chronous. The SCI offers the following principal features: s Full duplex synchronous and asynchronous operation. s Transmit, receive, line status, and device address interrupt generation. s Integral Baud Rate Generator capable of dividing the input clock by any value from 2 to 216-1 (16 bit word) and generating the internal 16X data sampling clock for asynchronous operation or the 1X clock for synchronous operation. s Fully programmable serial interface: – 5, 6, 7, or 8 bit word length. – Even, odd, or no parity generation and detec- tion. – 0, 1, 1.5, 2, 2.5, 3 stop bit generation. – Complete status reporting capabilities. – Line break generation and detection. s Programmable address indication bit (wake-up bit) and user invisible compare logic to support multiple microcomputer networking. Optional character search function. s Internal diagnostic capabilities: – Local loopback for communications link fault isolation. – Auto-echo for communications link fault isola- tion. s Separate interrupt/DMA channels for transmit and receive. s In addition, a Synchronous mode supports: – High speed communication – Possibility of hardware synchronization (RTS/ DCD signals). – Programmable polarity and stand-by level for data SIN/SOUT. – Programmable active edge and stand-by level for clocks CLKOUT/RXCL. – Programmable active levels of RTS/DCD sig- nals. – Full Loop-Back and Auto-Echo modes for DA- TA, CLOCKs and CONTROLs. Figure 75. SCI Block Diagram TRANSMIT BUFFER REGISTER REGISTER SHIFT TRANSMIT REGISTER SHIFT RECEIVER FUNCTION ALTERNATE REGISTER COMPARE ADDRESS REGISTER BUFFER RECEIVER DMA CONTROLLER CLOCK and BAUD RATE GENERATOR ST9 CORE BUS SOUT TXCLK/CLKOUT RXCLK SIN VA00169A Frame Control and STATUS DMA CONTROLLER RTS DCD SDS 9 |
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