ST24C01M6TR datasheet(8/16 Pages) STMICROELECTRONICS

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SCL

SDA

SCL

SDA

START

CONDITION

SDA

INPUT

SDA

CHANGE

AI00792

STOP

CONDITION

MSB

ACK

START

CONDITION

SCL

MSB

ACK

STOP

CONDITION

Figure 6. I2C Bus Protocol

Write Operations

The Multibyte Write mode (only available on the

ST24/25C01 and the ST24C01R versions) is se-

lected when the MODE pin is at VIH and the Page

Write mode when MODE pin is at VIL. The MODE

pin may be driven dynamically with CMOS input

levels.

Following a START condition the master sends a

device select code with the RW bit reset to ’0’. The

memory acknowledges this and waits for a byte

address. The byte address of 7 bits (the Most

Significant Bit is ignored) provides access to any of

the 128 bytes of the memory. After receipt of the

byte address the device again responds with an

acknowledge.

For the ST24/25W01 versions, any write command

with WC = 1 (during a period of time from the

START condition untill the end of the Byte Address)

will not modify data and will NOT be acknowledged

on data bytes, as in Figure 9.

Byte Write. In the Byte Write mode the master

sends one data byte, which is acknowledged by the

memory. The master then terminates the transfer

by generating a STOP condition. The Write mode

is independant of the state of the MODE pin which

could be left floating if only this mode was to be

used. However it is not a recommended operating

mode, as this pin has to be connected to either VIH

or VIL, to minimize the stand-by current.

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ST24/25C01, ST24C01R, ST24/25W01

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