ST20-GP1 datasheet(22/116 Pages) STMICROELECTRONICS

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ST20-GP1

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to-point links. The processor provides a number of operations to support message passing, the

most important being

in (input message) and out (output message).

The

in and out instructions use the address of the channel to determine whether the channel is

internal or external. This means that the same instruction sequence can be used for both hard and

soft channels, allowing a process to be written and compiled without knowledge of where its

channels are implemented.

Communication takes place when both the inputting and outputting processes are ready.

Consequently, the process which ﬁrst becomes ready must wait until the second one is also ready.

The inputting and outputting processes only become active when the communication has

completed.

A process performs an input or output by loading the evaluation stack with, a pointer to a message,

the address of a channel, and a count of the number of bytes to be transferred, and then executing

in or out instruction.

4.5

Timers

There are two 32-bit hardware timer clocks which ‘tick’ periodically. These are independent of any

on-chip peripheral real time clock. The timers provide accurate process timing, allowing processes

to deschedule themselves until a speciﬁc time.

One timer is accessible only to high priority processes and is incremented every microsecond,

cycling completely in approximately 4295 seconds. The other is accessible only to low priority

processes and is incremented every 64 microseconds, giving 15625 ticks in one second. It has a

full period of approximately 76 hours. All times are approximate due to the clock rate.

The current value of the processor clock can be read by executing a

ldtimer (load timer) instruction.

A process can arrange to perform a

tin (timer input), in which case it will become ready to execute

after a speciﬁed time has been reached. The

tin instruction requires a time to be speciﬁed. If this

time is in the ‘past’ then the instruction has no effect. If the time is in the ‘future’ then the process is

descheduled. When the speciﬁed time is reached the process becomes active. In addition, the

ldclock (load clock), stclock (store clock) instructions allow total control over the clock value and the

clockenb (clock enable), clockdis (clock disable) instructions allow each clock to be individually

stopped and re-started.

Figure 4.3 shows two processes waiting on the timer queue, one waiting for time 21, the other for

time 31.

Note, these timers stop counting when power-down mode (see Section 10.2 on page 61) is

invoked.

Function

ClockReg0

Current value of high priority (level 0) process clock

ClockReg1

Current value of low priority (level 1) process clock

TnextReg0

Indicates time of earliest event on high priority (level 0) timer queue

TnextReg1

Indicates time of earliest event on low priority (level 1) timer queue

TptrReg0

High priority timer queue

TptrReg1

Low priority timer queue

Table 4.2 Timer registers

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