ST21NFCA

Description

3/6

In addition, the embedded firmware and associated macrocells support handling and

protocol for the various interfaces:

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Single Wire Protocol (SWP) interface fully compliant with ETSI TS 102 613 Release 7

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SPI Slave interface fully compliant with Freescale specification

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Asynchronous Receiver Transmitter in master configuration supporting ISO/IEC 7816-3

T=0 and T=1 protocols

The ST21NFCA is a serial access circuit based on a 8/16-bit CPU core. Operations will be

synchronized with an internally generated clock issued by the Clock Generator module. The

internal speed of the device is fully software programmable.

The CPU includes the Arithmetic Logic Unit (ALU), the control logic and registers controlled

by the ST21NFCA firmware. The CPU interfaces with the on-chip RAM, ROM and EEPROM

memories via a 24-bit internal bus offering 16 MBytes of linear addressing space.

This device also includes a True Random Number Generator (TRNG), three 8-bit fully

programmable timers, a Cyclic Redundancy Check (CRC3309) module, and a Data

Encryption Standard (DES) accelerator.

Thanks to an enhanced power switch system, the ST21NFCA is able to support several

power supply sources ("Battery On", Battery Low and Battery Off" modes) which manages

the power management of the device and its associated UICC.

Figure 2.

ST21NFCA block diagram