LTC3336ACBZ-1-R7 datasheet(14/24 Pages) AD

14 / 24 page

LTC3336

Rev. A

For more information www.analog.com

OPERATION

Buck Regulator Dropout Operation

When the input supply voltage decreases towards the out-

put voltage, the rate of change of inductor current during

the upslope decreases, reducing the switching frequency

of the current bursts. Further reduction in input supply

voltage will eventually cause the P-channel MOSFET to

be turned on 100%, i.e., DC. The output voltage will then

be determined by the input voltage minus the voltage

drop across the P-channel MOSFET and the inductor. The

LTC3336 senses this state and enters a very low quiescent

current state.

Buck Regulator Output Overvoltage Condition and

Internal Clamp

An internal 1MΩ resistor pulls down VOUT if VOUT is

higher than 5% above its regulation voltage. This should

never happen in normal operation.

Buck Regulator Output Discharge

If EN is low, the buck regulator output is discharged

through an internal 10k resistor.

Table 2. Buck Regulator Output Voltage Selection via OUT[3:0] Pins

VOUT (V)

OUT3

OUT2

OUT1

OUT0

1.2

1.5

1.6

1.8

2.0

2.4

2.5

2.8

3.0

3.2

3.3

3.6

3.7

4.1

4.2

5.0

Note: Underlined voltage values of 1.2V, 1.8V, 2.5V, and 3V can be

set as power-up defaults. These voltage values can be “pin-strapped”

with a single pin tied high during start-up, while the other pins can be

dynamically set after start-up.

APPLICATIONS INFORMATION

Input Capacitor Selection

The input VIN should be bypassed with at least 0.1μF to

GND. In cases where the input voltage is from a battery

and the series resistance of the battery is high, a larger

capacitor may be required to handle transients. A larger

capacitor may also be necessary if the LTC3336 is sup-

plied with an input voltage close to 2.5V (at higher IPEAK

settings) to prevent the input voltage from transiently fall-

ing below the undervoltage lockout threshold.

Output Capacitor Selection

The duration for which the regulator sleeps depends on

the load current and the size of the output capacitor. The

sleep time decreases as the load current increases and/or

as the output capacitor decreases. The DC sleep hysteresis

window, Sleep Threshold – Wake-Up Threshold, is ±0.3%

around the programmed output voltage. Ideally this

means that the sleep time is determined by Equation 1.

tSLEEP = COUT • VOUT • 2 •

0.3%

ILOAD

⎛

⎝⎜

⎞

⎠⎟

(1)

As the output capacitor decreases to much lower val-

ues than described in Table 3, delays in the internal sleep

comparator along with the load current may result in the

VOUT voltage slewing past the ±0.3% thresholds. This will

lengthen the sleep time and increase VOUT ripple.

If transient load currents above the IPEAK setting are

required, then a larger capacitor can be used at the

output. This capacitor will be continuously discharged

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