AD4002 datasheet(32/39 Pages) AD

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AD4002/AD4006/AD4010

Data Sheet

Rev. A | Page 32 of 39

CS MODE, 3-WIRE WITH BUSY INDICATOR

This mode is typically used when a single AD4002/AD4006/

AD4010 device is connected to an SPI-compatible digital host

with an interrupt input (IRQ). The connection diagram is shown

in Figure 55, and the corresponding timing diagram is shown in

Figure 56.

Turbo mode must be disabled to use this mode. To disable turbo

mode, set the turbo mode enable field in the configuration

When performing conversions in this mode, SDI must be held

high. SDI can be connected to VIO if register reading and writing

is not required. A rising edge on CNV initiates a conversion and

forces SDO to high impedance. SDO remains high impedance

until the completion of the conversion, irrespective of the state of

CNV. Prior to the minimum conversion time, CNV can select

other SPI devices, such as analog multiplexers. However, CNV

must be returned low before the minimum conversion time (tCONV)

elapses and then held low for the maximum possible conversion

time to guarantee the generation of the busy signal indicator.

When the conversion is complete, the AD4002/AD4006/AD4010

then enter the acquisition phase and power-down. There must not

be any digital activity on the SCK during the conversion.

When the conversion is complete, SDO is driven low. With a pull-

up resistor (for example, 1 kΩ) on the SDO line, this transition

can be used as an interrupt signal to initiate the data reading

controlled by the digital host. The data bits are then clocked out

MSB first on SDO by subsequent SCK falling edges. The data is

valid on both SCK edges. Although the rising edge can capture

the data, a digital host using the SCK falling edge allows a faster

reading rate, provided it has an acceptable hold time, as dictated by

tHSDO (see Table 2). The conversion result is clocked out on SDO

on the first 18 SCK falling edges. If the status bits are enabled,

they are clocked out on SDO on the 19th through the 24th SCK

falling edges (see the Status Bits section). SDO returns to high

impedance after an optional additional SCK falling edge or the

next CNV rising edge (whichever occurs first).

If multiple AD4002/AD4006/AD4010 devices are selected at the

same time, the SDO output pin handles this contention without

damage or induced latch-up. It is recommended to keep this

contention as short as possible to limit extra power dissipation.

SDI1

SDO

CNV

SCK

CONVERT

DATA IN

CLK

DIGITAL HOST

VIO

IRQ

VIO

1kΩ

AD4002/

AD4006/

AD4010

1SDI MUST BE CONNECTED TO THE DIGITAL HOST DATA OUT

TO WRITE TO THE CONFIGURATION REGISTER

Figure 55. CS Mode, 3-Wire with Busy Indicator Connection Diagram

SDO

D17

D16

tDIS

SCK

tSCK

tSCKL

tSCKH

tHSDO

tDSDO

CNV

CONVERSION

ACQUISITION

tCONV

tCYC

ACQUISITION

SDI = 1

tCNVH

tACQ

tQUIET2

Figure 56. CS Mode, 3-Wire with Busy Indicator Serial Interface Timing Diagram (Status Bits Not Shown)

AD4002 Datasheet(PDF) 32 Page - Analog Devices

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