If UVP function is not required, the UVP pin must be left floating. In this case, noise immunity of the pin is

guaranteed by the internal pull-up IUVP_pull-up (1 uA, typ.) present in the UVP block.

If UVP function is required, RH value can be set arbitrarily, but some Mohms at least are recommended in order to

minimize the power consumption of the UVP network. Then, if Vin_UVP is the desired input undervoltage threshold,

the value of RL can be found from the following formula:

Equation 2

(2)

RL= VUVP_th

Vin_UVP−VUVP_th

RH

+IUVP_pull−up

Equation 3

(3)

PUVPVin = Vin2RH+RL

Thanks to the ultra-low consumption, the UVP pin can be used as an input to disable the SMPS from external,

reaching the lowest input power consumption while the SMPS is still connected to the AC mains but not delivering

power to its output.

The purpose of the UVP debounce time tUVP_DEB is also to guarantee some hold-up in case of a missing cycle of

the input line, as illustrated in Figure 33. Hold-up in case of input line missing cycles.

Figure 33. Hold-up in case of input line missing cycles

VUVP_th

1 missing cycle

VBULK

tUVP_DEB

VUVP

tUVP_DEB

2 missing cycles

IDRAIN

IC disabled

here

4.13

Overvoltage protection

If the voltage across OVP pin (VOVP) exceeds the internal threshold VOVP_th (4 V typ.) for a time greater than

tOVP_DEB (250 us, typ.), the PWM is disabled in autorestart for tOVP_REST time (500 ms, typ.), until VOVP falls

below VOVP_th.

The time interval tOVP_DEB is intended to filter out possible noises/disturbances of the line, which could affect the

correct operation of the function, and is obtained through an up/down counter, where tOVP_DEB is the time the

counter needs to reach its end-of-count (ovp_eoc) starting from zero and counting always up.

The operation is shown in Figure 34. OVP timing. When VOVP exceeds VOVP_th, the up/down OVP counter is

incremented.

If VOVP falls below VOVP_th before the OVP counter reaches ovp_eoc, the counter is decremented. If the count

goes down to zero, a disturbance on the OVP pin is assumed and there is no consequence on the IC behavior.

If VOVP stays above VOVP_th until the OVP counter reaches ovp_eoc: the PWM is disabled in autorestart for a

tOVP_REST time interval; the OVP counter is reset; VCC is maintained between VCson and VCcon by the periodical

activation of the internal HV-current source. If during the count-up VOVP falls below VOVP_th for some time, during

that time the counter is decremented and the PWM disable is delayed accordingly.

When VOVP drops below VOVP_th, the IC waits for the end of tOVP_REST, then restarts with soft-start phase.

VIPER31

General description

DS13285 - Rev 6

page 21/39