Motor de Búsqueda de Datasheet de Componentes Electrónicos
  Spanish  ▼
ALLDATASHEET.ES

X  

S2-LPSQTR Datasheet(PDF) 47 Page - STMicroelectronics

No. de pieza S2-LPSQTR
Descripción Electrónicos  Ultra-low power, high performance, sub-1 GHz transceiver
PDF  73 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

S2-LPSQTR Datasheet(HTML) 47 Page - STMicroelectronics

Back Button S2-LPSQTR Datasheet HTML 43Page - STMicroelectronics S2-LPSQTR Datasheet HTML 44Page - STMicroelectronics S2-LPSQTR Datasheet HTML 45Page - STMicroelectronics S2-LPSQTR Datasheet HTML 46Page - STMicroelectronics S2-LPSQTR Datasheet HTML 47Page - STMicroelectronics S2-LPSQTR Datasheet HTML 48Page - STMicroelectronics S2-LPSQTR Datasheet HTML 49Page - STMicroelectronics S2-LPSQTR Datasheet HTML 50Page - STMicroelectronics S2-LPSQTR Datasheet HTML 51Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 47 / 73 page
background image
Name
Addr
Default
Bit
Field name
Description
GPIO3_CONF
03
A2
01b: Digital input
10b: Digital
output low
power
11b: Digital
output high
power
SYNT3
05
42
7:5
PLL_CP_ISEL
Set the charge pump
current according to
the XTAL frequency
(see Table 30. Charge
pump words).
4
BS
Synthesizer band
select. This parameter
selects the out-of loop
divide factor of the
synthesizer:
0: 4, band select
factor for high
band
1: 8, band select
factor for middle
band.
3:0
SYNT[27:24]
MSB bits of the PLL
programmable divider.
SYNT2
06
16
7:0
SYNT[23:16]
Intermediate bits
of the PLL
programmable
divider (see
Section 4.3.1 RF
channel frequency
settings ).
SYNT1
07
27
7:0
SYNT[15:8]
Intermediate bits
of the PLL
programmable
divider (see
Section 4.3.1 RF
channel frequency
settings).
SYNT0
08
62
7:0
SYNT[7:0]
LSB bits of the
PLL programmable
divider (see
Section 4.3.1 RF
channel frequency
settings).
IF_OFFSET_ANA
09
2A
7:0
IF_OFFSET_ANA
Intermediate
frequency setting
for the analog RF
synthesizer, default:
300 kHz, see Eq. (14).
IF_OFFSET_DIG
0A
B8
7:0
IF_OFFSET_DIG
Intermediate
frequency setting for
the digital shift-to-
baseband circuits,
default: 300 kHz, see
Eq. (14).
CHSPACE
0C
3F
7:0
CH_SPACE
Channel spacing
setting, see Eq. (15).
S2-LPS
Register contents
DS13831 - Rev 1
page 47/73



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73


Datasheet Descarga

Go To PDF Page


Enlace URL



¿ALLDATASHEET es útil para Ud.?  [ DONATE ] 

Todo acerca de Alldatasheet   |   Publicidad   |   Contáctenos   |   Política de Privacidad   |   Enlace a la hoja de datos    |   Intercambio de Enlaces   |   Lista de Fabricantes
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com