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ST6G3240 Datasheet(PDF) 15 Page - STMicroelectronics

No. de pieza ST6G3240
Descripción Electrónicos  Dual supply level translator for dual memory cards (mini SD/micro SD managed NAND)
PDF  29 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST6G3240 Datasheet(HTML) 15 Page - STMicroelectronics

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ST6G3240
Electrical characteristics
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Table 11.
AC electrical characteristics (f = 10 MHz, 50% duty cycle(1))
VCCA = 1.5 V ±0.1 V
Paramete
r
From
(input)
To
(output)
VCCBn=1.8 V
± 0.15 V
VCCBn=2.5
V ± 0.2 V
VCCBn =3.0
± 0.3 V
VCCBn=3.3 V
± 0.3 V
Unit
Min
Max
Min
Max
Min
Max
Min
Max
tPLHAB,
tPHLAB
Propagation
delay time from
A to B
(CL= 15 pF,
RL=2kΩ)
CMD.h
nCMD
9
6
5.5
5.5
ns
CLK.h
nCLK
9
6
5.5
5.5
CLK.h
CLK-f
18
12
11
11
DATx.h nDATx
9
6
5.5
5.5
tPLHBA,
tPHLBA
Propagation
delay time from
B to A
(CL =7pF,
RL =2kΩ)
nCMD
CMD.h
9
999
ns
nDATx DATx.h
9
999
tPZL, tPZH
Output enable
time
(CL =7 pF,
RL =2kΩ)
INn
A
22
22
22
22
ns
Output enable
time
(CL =15 pF,
RL =2kΩ)
INn
Bn
22
222222
tPLZ, tPHZ
Output disable
time (CL=7 pF,
RL=2kΩ )
INn
A
33
33
33
33
ns
Output disable
time (CL=15pF,
RL=2kΩ)
INn
Bn
33
333333
tDIR, enable
DIR
A
8
888
ns
DIR
B
9
999
tDIR,
disable
DIR
A
7
777
ns
DIR
B
8
888
tOSLH,tOS
HL
Output to output
skew time(2)
1
111
ns
tCDLH,tCD
HL
Clock and data
skew time
1
111
ns
fmax
Clock
A
Bn
52
525252
MHz
Bn
A
52
525252
Data
A
Bn
104
104
104
104
Mbps
Bn
A
104
104
104
104
1.
Refer to figure 4.
2.
Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the
same device switching in the same direction, either High or Low ( tOSLH = | tPLHm - tPLHn |, tOSHL = | tPHLm – tPHLn | )



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