STMPE801

I2C module

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5.3

Start condition

A Start condition is identified by a falling edge of SDATA while SCLK is stable at high state.

A Start condition must precede any data/command transfer. The device continuously

monitors for a Start condition and will not respond to any transaction unless one is

encountered.

5.4

Stop condition

A Stop condition is identified by a rising edge of SDATA while SCLK is stable at high state.

A Stop condition terminates communication between the slave device and bus master. A

read command that is followed by NoAck can be followed by a Stop condition to force the

slave device into idle mode. When the slave device is in idle mode, it is ready to receive the

operation to registers.

5.5

Acknowledge bit

The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter

releases the SDATA after sending eight bits of data. During the ninth bit, the receiver pulls

the SDATA low to acknowledge the receipt of the eight bits of data. The receiver may leave

the SDATA in high state if it would to not acknowledge the receipt of the data.

5.6

Data input

The device samples the data input on SDATA on the rising edge of the SCLK. The SDATA

signal must be stable during the rising edge of SCLK and the SDATA signal must change

only when SCLK is driven low.