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DIO6012 Datasheet(PDF) 8 Page - DIOO MICROCIRCUITS CO., LTD

No. de pieza DIO6012
Descripción Electrónicos  High-Efficiency 1 MHz, 2 A Output Synchronous Step Down Converter
PDF  13 Pages
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Fabricante Electrónico  DIOO [DIOO MICROCIRCUITS CO., LTD]
Página de inicio  https://www.dioo.com/#/
Logo DIOO - DIOO MICROCIRCUITS CO., LTD

DIO6012 Datasheet(HTML) 8 Page - DIOO MICROCIRCUITS CO., LTD

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DIO6012
www.dioo.com
© 2023 DIOO MICROCIRCUITS CO., LTD
DIO6012• Rev. 2.0
Application Information
DIO6012 is a synchronous buck regulator IC that integrates the PWM control, top and bottom switches on the
same die to minimize the switching transition loss and conduction loss. With ultra low RDS(ON) power switches
and proprietary PWM control, this regulator IC can achieve the highest efficiency and the highest switch
frequency simultaneously to minimize the external inductor and capacitor size, and thus achieving the
minimum solution footprint.
Because of the high integration in the DIO6012 IC, the application circuit based on this regulator IC is rather
simple. Only input capacitor CIN, output capacitor COUT, output inductor L and feedback resistors (R1 and R2)
need to be selected for the targeted applications specifications.
Feedback resistor dividers R1 and R2
Choose R1 and R2 to program the proper output voltage. To minimize the power consumption under light
loads, it is desirable to choose large resistance values for both R1 and R2. A value of between 10k and 1M is
highly recommended for both resistors. If VOUT is 1.8 V, R1 = 100 k is chosen, then R2 can be calculated to be
50k.
R2=
1
6
.
0
6
.
0
R
V
V
V
OUT
(1)
Input capacitor CIN
This ripple current through input capacitor is calculated as:
ICIN_RMS=IOUT
)
1
( D
D 
(2)
This formula has a maximum at VIN = 2 VOUT condition, where ICIN_RMS = IOUT/2. This simple worst-case
condition is commonly used for DC/DC design.
With the maximum load current at 1.2 A. A typical X5R or better grade ceramic capacitor with 6 V rating and
more than 1pcs 10 uF capacitor can handle this ripple current well. To minimize the potential noise problem,
place this ceramic capacitor really close to the IN and GND pins. Care should be taken to minimize the loop
area formed by CIN, and IN/GND pins.



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