M58MR032C datasheet(10/52 Pages) STMICROELECTRONICS

10 / 52 page

M58MR032C, M58MR032D

10/52

Reset/Power-down. The memory is in Power-

down when the Read Configuration Register is set

for Power-down and RP is at VIL. The power con-

sumption is reduced to the Power-down level, and

Outputs are in high impedance, independent of the

Chip Enable E, Output Enable G or Write Enable

W inputs. The memory is in reset when the Read

Configuration Register is set for Reset and RP is

at VIL. The power consumption is the same of the

standby and the outputs are in high impedance.

After a Reset/Power down the device defaults to

read array mode, the status register is set to 80h

and the read configuration register defaults to

asynchronous read.

Block Locking. Any combination of blocks can

be temporarily protected against Program or

Erase by setting the lock register and pulling WP

to VIL. The following summarizes the locking oper-

ation. All blocks are protected on power-up. They

can then be unprotected or protected with the Un-

protect and Protect commands. The Lock com-

mand protects a block and prevents it from being

unlocked when WP = 0. When WP = 1, Lock is

overridden. Lock is cleared only when the device

is reset or powered-down (see Protect instruction).

Table 9. Identifier Codes

Note: 1. DRC means Die Revision Code.

CR means Read Configuration Register.

LPR means Lock Protection Register.

PR means Unique Device Number and User Programmable OTP.

Code

Address (h)

Data (h)

Manufacturer Code

Bank Address + 00

0020

Device Code

Top

Bank Address + 01

88DA

Bottom

Bank Address + 01

88DB

Block Protection

Protected and Unlocked

Bank Address + 02

0001

Unprotected and Unlocked

0000

Protected and Locked

0003

Unprotected and Locked

0002

Die Revision Code

Bank Address + 03

DRC (1)

Read Configuration Register

Bank Address + 05

CR (1)

Lock Protection Register

Bank Address + 80

LPR (1)

Protection Register

Bank Address + 81

Bank Address + 88

PR (1)

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