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USB2226 Datasheet(PDF) 9 Page - SMSC Corporation |
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USB2226 Datasheet(HTML) 9 Page - SMSC Corporation |
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9 / 23 page ![]() Chapter 4 Block Diagram Figure 4.1 USB2226 Block Diagram USB 2.0 PHY ( Transceiver ) FAST 8051 CPU CORE GPIO Configuration and Control Clock Generation SIE ( Serial Interface Engine ) Interrupt Controller Latch phase 0, 2 SIE Latch phase 3 8051 Latch phase 1 FMC 60M Hz 32 Bit Osc Address 64 Bytes EP 0TX 64 Bytes EP 0RX 64 Bytes EP 1TX 64 Bytes EP 1RX Auto address generators Data @ 32 bit 15Mhz SIE Control Regs EP0RX_BC RAMRD _A/B EP0TX_BC RAMW R _A/B CLOCKOUT 24 MHz 512 Bytes EP 2 TX/RX Buffer A 1.25KB SRAM 12K Byte Scratchpad SRAM Clocked by Phase 0, 2 Clock Clocked by Phase 3 Clock 512 Bytes EP 2 TX/RX Buffer B Mem ory Cards Scratchpad SRAM (768 Byte) ECC SD Controller SD/MMC Flash Media Controllers (FMC) MS/HS MS/MS PRO SM/SSFDC CF Control/ Status CRC MEM /IO Bus 29pins DATA DATA DATA DATA CRC EP1TX_BC EP1RX_BC Flash M edia DM A Unit 64K ROM PW R _FET0 PW R _FET1 PW R_FET2 SM /xD_PW R MS _PW R SD /MMC _PW R M E M / IO B u s 2 9 P i n s M EM/IO Bus 29 pins Address Address Address Address Address Address 32 bit 15MHz Data Buss M EM/IO Bus 29 Pins Control/ Status Control/ Status Control/ Status MS Controller SM Controller CF Controller Control/ Status |
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