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LRI64 Datasheet(PDF) 16 Page - STMicroelectronics

No. de pieza LRI64
Descripción Electrónicos  Memory tag IC at 13.56 MHz, with 64-bit unique ID and WORM user area, ISO 15693 and ISO 18000-3 Mode 1 compliant
PDF  52 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

LRI64 Datasheet(HTML) 16 Page - STMicroelectronics

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LRI64 to VCD frames
LRI64
16/52
9
LRI64 to VCD frames
Response frames are delimited by a start of frame (SOF) and an end of frame (EOF) and
are implemented using a code violation mechanism. The LRI64 supports these in the one
subcarrier mode, at the fast data rate, only.
The VCD is ready to receive a response frame from the LRI64 before 320.9µs (t1) after
having sent a command frame.
9.1
LRI64 SOF
SOF comprises three parts: (see Figure 11)
●
an unmodulated period of 56.64 µs,
●
24 pulses of 423.75 kHz (fc/32),
●
a logic 1 which starts with an unmodulated period of 18.88 µs followed by 8 pulses of
423.75 kHz.
9.2
LRI64 EOF
EOF comprises three parts: (see Figure 12)
●
a logic 0 which starts with 8 pulses of 423.75 kHz followed by an unmodulated period of
18.88 µs.
●
24 pulses of 423.75 kHz (fC/32),
●
an unmodulated time of 56.64 µs.
Figure 11.
Response SOF, using high data rate and one subcarrier
Figure 12.
Response EOF, using high data rate and one subcarrier
AI06671B
113.28 µs
37.76 µs
AI06675B
113.28 µs
37.76 µs



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