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93LC66 Datasheet(PDF) 12 Page - Microchip Technology |
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93LC66 Datasheet(HTML) 12 Page - Microchip Technology |
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12 / 22 page ![]() DS00560D-page 12 © 1994 Microchip Technology Inc. Using the 93LC56 and 93LC66 0061 000A eeprom equ 0ah ; bit buffer 0062 000C addr equ 0ch ; address register 0063 000D datai equ 0dh ; stored data input reg. 0064 000E datao equ 0eh ; stored data output reg. 0065 0010 txbuf equ 10h ; transmit buffer 0066 0011 count equ 11h ; bits transmitted so far 0067 0012 bits equ 12h ; bits to transmit 0068 0013 bytcnt equ 13h ; byte counter for write routine 0069 0015 loops equ 15h ; delay loop counter 0070 0016 loops2 equ 16h ; delay loop counter 0071 ;************************************************************ 0072 ; Bit Assignments 0073 ;************************************************************ 0074 0007 di equ 7 ; eeprom input 0075 0006 do equ 6 ; eeprom output 0076 0007 datout equ 7 ; data out line (port_b) 0077 0006 datin equ 6 ; data in line (port_b) 0078 0005 sclk equ 5 ; clock line (port_b) 0079 0004 chpsel equ 4 ; chip select line (port_b) 0080 0001 timeout equ 1 ; write cycle timeout warning (port_a) 0081 ; 0082 ;************************************************************* 0083 0000 org 01ffh 0084 01FF 0A26 begin goto PWRUP ; set the reset vector 0085 0000 org 000h 0086 0000 0A26 goto PWRUP 0087 ; 0088 ;************************************************************* 0089 ; DATA POLL DELAY ROUTINE 0090 ; This routine delays 100 us is 0091 ; used for delay between polls 0092 ;************************************************************* 0093 dpdelay 0094 ; 0095 0001 0C19 movlw .25 ; timing adjustment variable 0096 0002 0036 movwf loops2 0097 0003 0000 top nop 0098 0004 02F6 decfsz loops2 ; loops complete? 0099 0005 0A03 goto top ; no, go again 0100 ; 0101 0006 0800 retlw 0 ; yes, return from sub 0102 ; 16c5x/7x Cross-Assembler V4.12 Released Mon Jun 06 10:49:00 1994 Page 3 Line PC Opcode 0103 ;************************************************************** 0104 ; Start Bit Subroutine 0105 ; this routine generates a start bit 0106 ; (Chip select and DI high when clock goes high) 0107 ;**************************************************************; 0108 BSTART 0109 0007 04C6 bcf port_b,datin ; set datain and chipselect lines 0110 0008 0486 bcf port_b,chpsel ; low just to check operation 0111 0009 04A6 bcf port_b,sclk ; make sure clock starts low too. 0112 000A 0000 nop 0113 ; 0114 000B 0586 bsf port_b,chpsel ; set chip select line high 0115 000C 05C6 bsf port_b,datin ; set data in line high 0116 000D 0000 nop 0117 000E 05A6 bsf port_b,sclk ; set the clock line high to 0118 ; generate the start bit 0119 000F 0000 nop 0120 0010 0000 nop 0121 0011 04A6 bcf port_b,sclk ; set clock low again 0122 0012 0800 retlw 0 0123 ; 0124 ;************************************************************* 8-110 |
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