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M48T248Y Datasheet(PDF) 11 Page - STMicroelectronics |
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M48T248Y Datasheet(HTML) 11 Page - STMicroelectronics |
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11 / 24 page ![]() 11/24 M48T248Y, M48T248V Figure 8. Memory WRITE Cycle 2 Note: 1. OE = VIH or VIL. If OE = VIH during a WRITE cycle, the output buffers remain in a high impedance state. 2. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers remain in a high impedance state during this period. AI04232 DQ0–DQ7 ADDRESSES WE CE DATA IN STABLE tWR tOEW tWC tODW tDS tDH tCOE tWP tAW |
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