Application information

L4993

16/30

3.2

Reset

The reset circuit supervises the output voltage Vo. The Vo_th reset threshold is defined with

the in-ternal reference voltage and a resistor output divider. If the output voltage becomes

lower than Vo_th then Res goes low with a reaction time trr. The reset low signal is

guaranteed for an output voltage Vo greater than 1V.

When the output voltage becomes higher than Vo_th then Res goes high with a delay trd.

This delay is obtained by an internal oscillator.

The oscillator period is given by:

Tosc = [(Vrhth-Vrlth) x Ctr] / Icr + [(Vrhth-Vrlth) x Ctr] / Idr

where:

Icr:

is an internally generated charge current

Idr:

is an internally generated discharge current

Vrhth, Vrlth:

are two voltages defined with the output voltage and a resistor output

divider

Ctr:

is an external capacitance.

trd is given by:

trd = 512 x Tosc

Reset is active when En is high.

Figure 26.

Reset timing diagram

Wi

Vo

Vcr

Res

<

trr

trr

Tosc

trd = 512 Tosc

Vout_th

Vrhth

Vrlth