ISLA224P12

FN7983 Rev.4.01

Page 10 of 32

Apr 8, 2024

LVDS INPUTS (CLKDIVRSTP, CLKDIVRSTN)

Input Common Mode Range

VICM

825

1575

mV

Input Differential Swing (Peak-to-peak, Single-ended)

VID

250

450

mV

CLKDIVRSTP Input Pull-down Resistance

RIpd

100

k



CLKDIVRSTN Input Pull-up Resistance

RIpu

100

k



LVDS OUTPUTS

Differential Output Voltage (Note 10)VT

3mA Mode

612

mVP-P

Output Offset Voltage

VOS

3mA Mode

1120

1150

1200

mV

Output Rise Time

tR

240

ps

Output Fall Time

tF

240

ps

CMOS OUTPUTS

Voltage Output High

VOH

IOH = -500µA

OVDD - 0.3 OVDD - 0.1

V

Voltage Output Low

VOL

IOL = 1mA

0.1

0.3

V

Output Rise Time

tR

1.8

ns

Output Fall Time

tF

1.4

ns

NOTES:

9. The Tri-Level Inputs internal switching thresholds are approximately. 0.43V and 1.34V. It is advised to float the inputs, tie to ground or AVDD depending

on desired function.

10. The voltage is expressed in peak-to-peak differential swing. The peak-to-peak singled-ended swing is 1/2 of the differential swing.

Digital Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)

PARAMETER

SYMBOL

CONDITIONS

MIN

(Note 5)TYP

MAX

(Note 5)UNITS

Timing Diagrams

FIGURE 3. LVDS

CLKN

CLKP

INP

INN

tA

CLKOUTN

CLKOUTP

tCPD

D[13:0]N

D[13:0]P

LATENCY = L CYCLES

tDC

tPD

A DATA

N-L

B DATA

N-L

A DATA

N-L+1

B DATA

N-L+1

B DATA

N-1

A DATA

N

B DATA

N