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IMX93CEC Datasheet(PDF) 49 Page - NXP Semiconductors |
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IMX93CEC Datasheet(HTML) 49 Page - NXP Semiconductors |
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49 / 123 page ![]() RADIN RAS CAS VAS ZAS ZADIN VADIN CADIN Pad leakage due to input protection ADC SAR ENGINE INPUT PIN INPUT PIN INPUT PIN SIMPLIFIED CHANNEL SELECT CIRCUIT SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT RADIN RADIN RADIN Ilkg RIOMUX CP Figure 21. ADC input impedance equivalent circuit diagram 4.12 External peripheral interface parameters The following subsections provide information on external peripheral interfaces. 4.12.1 Ultra-high-speed SD/SDIO/MMC host interface (uSDHC) AC timing This section describes the electrical information of the uSDHC, which includes SD/eMMC5.1 (single data rate) timing, eMMC5.1/ SD3.0 (dual data rate) timing and SDR50/SDR104 AC timing. The DSE[5:0] = 001111 and FSEL1[1:0] = 11 are required drive settings to meet the timing. 4.12.1.1 SD3.0/eMMC5.1 (single data rate) AC timing Figure 22 depicts the timing of SD3.0/eMMC5.1, and Table 53 lists the SD3.0/eMMC5.1 timing characteristics. NXP Semiconductors IMX93CEC i.MX 93 Applications Processors Data Sheet for Commercial Products IMX93CEC All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 7 — 12 February 2026 Document feedback 49 / 123 |
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