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SMS01GAF Datasheet(PDF) 43 Page - Numonyx B.V |
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SMS01GAF Datasheet(HTML) 43 Page - Numonyx B.V |
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43 / 61 page  SMSxxxAF, SMSxxxFF, SMSxxxBF Serial peripheral interface (SPI) mode 43/61 Figure 31. SD Memory Card System SPI Mode Bus Topology 7.2 SPI Bus Protocol Whereas the SD channel is based on command and data bit streams initiated by a start bit and terminated by a stop bit, the SPI channel is Byte-oriented. Every command or data block is built up with 8-bit Bytes and is Byte-aligned to the CS signal (that is, the length is a multiple of 8 clock cycles). Like in the SD protocol, messages in the SPI protocol consist of command, response and data-block tokens. All communications between host and cards are controlled by the host (master). The host starts every bus transaction by asserting the CS signal Low. The response behaviors in SPI mode and SD mode differ in three ways. In the SPI mode: ● the selected card always responds to the command. ● two additional (8 & 16 bit) response structures are used ● when the card encounters a data retrieval problem, it sends an error response in place of the expected data block (in the SD mode the card does not respond but implements a timeout). In addition to returning a response for every command received, the card returns a special data response token for every data block received during write operations. 7.2.1 Mode Selection The SD Memory Card wakes up in the SD mode. It will enter the SPI mode if the CS signal is asserted (Low) when the Reset command (CMD0) is received. The only way to return to the SD mode is to start a new power-down/power-up sequence. In SPI mode, the SD Card protocol state machine does not apply. CS(A) VDD VSS CS VDD VSS CLK, DataIN, DataOut SD Memory Card (A) (SPI mode) CS VDD VSS CLK, DataIN, DataOut SD Memory Card (B) (SPI mode) CLK DataIN DataOut CS VDD VSS CLK, DataIN, DataOut MultiMediaCard (C) (SPI mode) ai10065 HOST CS(B) CS(B) |
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