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APEX20KC Datasheet(PDF) 65 Page - Altera Corporation

No. de pieza APEX20KC
Descripción Electrónicos  Programmable Logic Device
PDF  90 Pages
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Fabricante Electrónico  ALTERA [Altera Corporation]
Página de inicio  http://www.altera.com
Logo ALTERA - Altera Corporation

APEX20KC Datasheet(HTML) 65 Page - Altera Corporation

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Altera Corporation
65
APEX 20KC Programmable Logic Device Data Sheet
Timing Model
The high-performance FastTrack and MegaLAB interconnect routing
resources ensure predictable performance, accurate simulation, and
accurate timing analysis. This predictable performance contrasts with that
of FPGAs, which use a segmented connection scheme and therefore have
unpredictable performance.
Figure 32 shows the fMAX timing model for APEX 20KC devices.
Figure 32. fMAX Timing Model
Figures 33 and 34 show the asynchronous and synchronous
timingwaveforms, respectively, for the ESB macroparameters in Table 37.
SU
H
CO
LUT
t
t
t
t
F1—4
F5—20
F20+
LE
ESB
Routing Delay
t
t
t
t
ESBARC
t
ESBSRC
t
ESBAWC
t
ESBSWC
t
ESBWASU
t
ESBWDSU
t
ESBSRASU
t
ESBWESU
t
ESBDATASU
t
ESBWADDRSU
t
ESBRADDRSU
t
ESBDATACO1
t
ESBDATACO2
t
ESBDD
t
PD
t
PTERMSU
t
PTERMCO



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