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LRI512 Datasheet(PDF) 11 Page - STMicroelectronics

No. de pieza LRI512
Descripción Electrónicos  Memory TAG IC 512 bit High Endurance EEPROM 13.56MHz, ISO 15693 Standard Compliant with E.A.S.
PDF  54 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

LRI512 Datasheet(HTML) 11 Page - STMicroelectronics

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LRI512
LRI512 TO VCD FRAMES
Frames are delimited by an SOF and EOF and are
implemented using code violation. Unused options
are reserved for future use.
For the low data rate, the same subcarrier fre-
quency or frequencies are used. In this case the
number of pulses shall be multiplied by 4.
The VCD is ready to receive a response frame
from the LRI512 within less than t1 after having
sent a command frame (as specified in Table 59).
SOF When Using One Subcarrier
High Data Rate. SOF comprises 3 parts: (see
Figure 20)
– an unmodulated time of 56.64 µs,
– 24 pulses of 423.75 kHz (
fc/32),
– a logic 1 which starts with an unmodulated time
of 18.88 µs followed by 8 pulses of 423.75 kHz.
Low Data Rate. SOF comprises 3 parts: (see
Figure 21)
– an unmodulated time of 226.56 µs,
– 96 pulses of 423.75 kHz (
fc/32),
– a logic 1 which starts with an unmodulated time
of
75.52 µs
followed
by
32
pulses
of
423.75 kHz.
Figure 20. Start of Frame, High Data Rate, One Subcarrier
Figure 21. Start of Frame, Low Data Rate, One Subcarrier
AI06671
113.28 µs
37.76 µs
AI06672
453.12 µs
149.86 µs (ISO=151.04 µs)



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