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DESCRIPTION/ORDERING INFORMATION (CONTINUED)

DIR1

A1

OE

B1

SN74AVC4T774

4-BIT DUAL-SUPPLY BUS TRANSCEIVER

WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS

SCES693A – FEBRUARY 2008 – REVISED FEBRUARY 2008

The SN74AVC4T774 is designed for asynchronous communication between data buses. The logic levels of the

direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port

outputs or place both output ports in the high-impedance mode. The device transmits data from the A bus to the

B bus when the B outputs are activated, and from the B bus to the A bus when the A outputs are activated. The

input circuitry on both A and B ports is always active and must have a logic HIGH or LOW level applied to

The SN74AVC4T774 is designed so that the control pins (DIR1, DIR2, DIR3, DIR4, and OE) are supplied by

preventing damaging current backflow through the device when it is powered down.

state.

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Since this device has CMOS inputs, it is very important to not allow them to float. If the inputs are not driven to

the input voltage settlement is governed by many factors (e.g. capacitance, board-layout, package inductance,

surrounding conditions, etc.), ensuring that they these inputs are kept out of erroneous switching states and tying

them to either a high or a low level minimizes the leakage-current.

FUNCTION TABLE

(Each Bit)

CONTROL INPUTS

OUTPUT CIRCUITS

OPERATION

OE

DIR

A PORT

B PORT

L

L

Enabled

Hi-Z

B data to A data

L

H

Hi-Z

Enabled

A data to B data

H

X

Hi-Z

Hi-Z

Isolation

LOGIC DIAGRAM (POSITIVE LOGIC)(1)

(1)

Shown for a single channel

2

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