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ST7FLCD1 Datasheet(PDF) 59 Page - STMicroelectronics |
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ST7FLCD1 Datasheet(HTML) 59 Page - STMicroelectronics |
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59 / 95 page  59/95 ST7FLCD1 I²C Single-Master Bus Interface Bits [5:0] = CC[5:0] 6-bit clock divider. These bits select the speed of the bus (fSCL) depending on the I²C mode. They are not cleared when the interface is disabled (PE = 0). The value of the 6-bit clock divider, CC[5:0] ≥ 03h Fast mode (FM/SM = 0): fSCL > 100 kHz fSCL = fCPU/([2x([CC5...CC0]+3)]+1) Standard mode (FM/SM = 1): fSCL ≤100 kHz fSCL = fCPU/(3x([CC5...CC0]+3)) Note: The programmed fSCL speed assumes that there is no load on the SCL and SDA lines. I²C DATA REGISTER (I2CDR) Read / Write Reset Value: 0000 0000 (00h) Bits [7:0] = D[7:0] 8-bit Data Register. These bits contain the byte to be received or transmitted on the bus. Transmitter mode: Bytes are automatically transmitted when the software writes to the DR register. Receiver mode: The first data byte is automatically received in the DR register using the least significant bit of the address. Then, the subsequent data bytes are received one-by-one after reading the DR register. 765 432 10 D7 D6 D5 D4 D3 D2 D1 D0 |
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