TMS320C6000GDPA167 datasheet(49/148 Pages) TI

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TMS320C6713

FLOATINGPOINT DIGITAL SIGNAL PROCESSOR

SPRS186L − DECEMBER 2001 − REVISED NOVEMBER 2005

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

Terminal Functions (Continued)

SIGNAL

PIN NO.

TYPE†

IPD/

IPU‡

DESCRIPTION

NAME

PYP

GDP

TYPE†

IPD/

IPU‡

DESCRIPTION

RESETS AND INTERRUPTS

RESET

176

A13

IPU

Device reset. When using Boundary Scan mode, drive the EMU[1:0] and

RESET pins low.

NMI

175

C13

IPD

Nonmaskable interrupt

• Edge-driven (rising edge)

Any noise on the NMI pin may trigger an NMI interrupt; therefore, if the NMI pin is

not used, it is recommended that the NMI pin be grounded versus relying on the

IPD.

GP[7](EXT_INT7)

General-purpose input/output pins (I/O/Z) which also function as external

interrupts

GP[6](EXT_INT6)

interrupts

• Edge-driven

Polarity independently selected via the External Interrupt Polarity Register

GP[5](EXT_INT5)/

AMUTEIN0

I/O/Z

IPU

• Polarity independently selected via the External Interrupt Polarity Register

bits (EXTPOL.[3:0]), in addition to the GPIO registers.

GP[4] and GP[5] pins also function as AMUTEIN1 McASP1 mute input and

GP[4](EXT_INT4)/

AMUTEIN1

GP[4] and GP[5] pins also function as AMUTEIN1 McASP1 mute input and

AMUTEIN0 McASP0 mute input, respectively, if enabled by the INEN bit in the

associated McASP AMUTE register.

HOST-PORT INTERFACE (HPI)

HINT/GP[1]

135

J20

O/Z

IPU

Host interrupt (from DSP to host) (O) [default] or this pin can be programmed as

a GP[1] pin (I/O/Z).

HCNTL1/AXR1[1]

144

G19

IPU

Host control − selects between control, address, or data registers (I) [default] or

McASP1 data pin 1 (I/O/Z).

HCNTL0/AXR1[3]

146

G18

IPU

Host control − selects between control, address, or data registers (I) [default] or

McASP1 data pin 3 (I/O/Z).

HHWIL/AFSR1

139

H20

IPU

Host half-word select − first or second half-word (not necessarily high or low

order) (I) [default] or McASP1 receive frame sync or left/right clock (LRCLK)

(I/O/Z).

HR/W/AXR1[0]

143

G20

IPU

Host read or write select (I) [default] or McASP1 data pin 0 (I/O/Z).

† I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal

‡ IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors

no greater than 4.4 k

Ω and 2.0 kΩ, respectively.]

TMS320C6000GDPA167 Datasheet(PDF) 49 Page - Texas Instruments

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