MPF0900AMMA2ES datasheet(43/205 Pages) NXP

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NXP Semiconductors

PF09

Nine-channel power management IC with advanced system safety monitoring

aaa-056051

RESET_CNT

RESET EVENT

n = RESET_MAX

RESET_CNT reset

on LPOFF

RESET_CNT reset

by MCU

Fail-safe

TRANSITION

RESET EVENT

Figure 12. Reset counter strategy.

The device can bypass the cyclic reset failure by setting the RESET_MAX[3:0] = 0x00. In this scenario, the

PMIC will be able to keep generating reset events, however, the device will never be able to proceed to a fault

shutdown.

If the cyclic reset failure is bypassed, the RESET_CNT[3:0] value will still be increased for every reset event

until it reaches the maximum count (0b1111), and it will keep that value until the counter is reset manually or

when the device crosses into the LPOFF state.

12.4.3 Early warning

When a power down is initiated due to a fault condition, an EWARN_I interrupt will be set, and the INTB pin will

be asserted before it starts the Power-down sequence.

The following fault modes will generate an EWARN interrupt:

• Fault timer expired

• FAULT_CNT = FAULT_MAX_CNT

• Thermal shutdown (TJ > TSD)

• A hard reset event

• A VIN_OV event when VIN_OV_SDWN=1

• A turn-off event due to RSTB being asserted externally

The OTP_EWARN_TIME[1:0] allows the user to select a time delay from when the EWARN interrupt is

generated and the power-down sequence is started.

PF09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.3 — 16 December 2025

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MPF0900AMMA2ES Datasheet(PDF) 43 Page - NXP Semiconductors