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MPC7448 Datasheet(PDF) 38 Page - Freescale Semiconductor, Inc |
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MPC7448 Datasheet(HTML) 38 Page - Freescale Semiconductor, Inc |
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38 / 60 page  MPC7448 RISC Microprocessor Hardware Specifications, Rev. 4 38 Freescale Semiconductor System Design Information These requirements are shown graphically in Figure 16. Figure 16. MPC7448 Power Up Sequencing Requirements Certain stipulations also apply to the manner in which the power rails of the MPC7448 power down, as follows: •OVDD may ramp down any time before or after VDD. • The voltage at the SYSCLK input must not exceed VDD once VDD has ramped down below 0.9 V. • The voltage at the SYSCLK input must not exceed OVDD by more 20% during transients (see overshoot/undershoot specifications in Figure 2) or 0.3 V DC (see Table 2) at any time. AVDD VDD OVDD SYSCLK 0.9 V no restrictions between OVDD and VDD 0.9 V limit imposed by VDD if OVDD ramps up first limit imposed by OVDD if VDD ramps up first 100 μs (nominal) delay from VDD to AVDD |
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